1. Field of the Invention
The present invention relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2009-257151, filed Nov. 10, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, miniaturization of planar transistors has been reaching its limit. For this reason, vertical transistors have been proposed for higher integration of semiconductor devices.
FIG. 9A is a plan view illustrating a vertical pillar transistor of a related art. FIG. 9B is a cross-sectional view taken along line B-B′ shown in FIG. 9A. As shown in FIG. 9A, the vertical pillar transistor includes: a silicon substrate 101; a first silicon pillar 102 extending from a main surface 101a of the silicon substrate 101; and a second silicon pillar (dummy pillar) 104 extending from the main surface 101a of the silicon substrate 101, the second silicon pillar 104 being close to the first silicon pillar 102. An insulating film 103 for element isolation fills a recess 101c in the semiconductor substrate 101.
A gate insulating film 105 covers a side surface of the first silicon pillar 102. A gate electrode 106 covers the gate insulating film 105. An upper diffusion layer 113 partially covers an upper surface of the first silicon pillar 102. A lower diffusion layer 114 is positioned in the silicon substrate 101, adjacent to a bottom surface of the first silicon pillar 102.
An insulating film 163 covers a side surface of the second side pillar 104. A connecting electrode 160 covers the insulating film 163. The connecting electrode 160 is connected to the gate electrode 106 via a connecting portion 160c. 
Although not shown, an inter-layer insulating film covers the first and second silicon pillars 102 and 104. A first contact 110 penetrates the inter-layer insulating film so as to be connected to the connecting electrode 160. A voltage can be applied to the gate electrode 106 through the contact 110.
A second contact 111 penetrates the inter-layer insulating film so as to be connected to the upper diffusion layer 113. A third contact 112 penetrates the inter-layer insulating film so as to be connected to the lower diffusion layer 114. A nitride film 175 covers an upper surface of the insulating film 103.
As shown in FIG. 9A, the first silicon pillar 102 is positioned in substantially the center of a region defined by the nitride film 175, which is substantially rectangular in plan view. The gate insulating film 105 surrounds the first silicon pillar 102. A nitride film 109, which is substantially circular in plan view, covers an upper surface of the gate insulating film 105 and a part of the upper surface of the first silicon pillar 102. The gate electrode 106 surrounds the gate insulating film 105 and the nitride film 109 in plan view.
A nitride film 172, which is substantially rectangular in plan view, covers an upper surface of the second silicon pillar (dummy pillar) 104. The connecting electrode 160 surrounds the second silicon pillar 104 and the nitride film 172 in plan view. The connecting electrode 160 is in contact with the gate electrode 106 at the connecting portion 160c. The first to third contacts 110, 111, and 112 are separately aligned on a center line of the rectangular region, which extends in the longitudinal direction. The center line passes the centers of the first to third contacts 110, 111, and 112.
As shown in FIG. 9B, an insulating film 163 insulates the second silicon pillar 104 from the connecting electrode 160. Further, the insulating film 163 and the nitride film 172 cover the upper surface of the second silicon pillar 104. For this reason, although the first contact 110 is in contact with the connecting electrode 160, the first contact 110 is insulated from the second silicon pillar 104, thereby preventing a short circuit between the first contact 110 and the second silicon pillar 104.
According to the method of the related art for manufacturing the vertical pillar transistor, however, the second silicon pillar 104 is formed close to the first silicon pillar such that the gate electrode 106 is in contact with the connecting electrode 160 by self-alignment. For this reason, it is difficult to form a contact hole for forming the first contact 110 at a predetermined position, with a predetermined size and depth. Further, the insulating film 163 and the nitride film 172 are so thin that there is little etching margin in the depth direction. For this reason, it is difficult to control a depth of the contact hole.
Consequently, the contact hole penetrates the insulating film 163 and the nitride film 172 so that the second silicon pillar is partially or fully exposed in some cases. In this case, the first contact 110 is in contact with the second silicon pillar 104, thereby causing a short circuit between the first contact 110 and the silicon substrate 101, and therefore degrading a manufacturing yield of the vertical transistor.
Japanese Patent Laid-Open Publication No. 2004-319808 discloses a method of manufacturing an MIS field-effect transistor which includes anisotropically dry-etching a PSG (Phospho-Silicate Glass) film, which is formed by chemical vapor deposition, to selectively form a via hole. Japanese Patent Laid-Open Publication No. 2008-159972 discloses a method of manufacturing a semiconductor device which includes adjusting an etching condition to adjust a height of the gate electrode. Japanese Patent Publication No. 3371708 discloses a method of manufacturing a vertical field-effect transistor which includes: forming a contact hole in an inter-layer insulating film; and forming a contact plug, which is made of tungsten or the like, so as to fill the contact hole. However, any of the related art can solve the above problems.